In order to increase speeds of memory operations, Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) devices (also referred to as DDR memory devices), have been developed so that data is written to and/or read from the memory device on both rising and falling edges of a main clock signal. In known DDR memory devices, both the main clock signal and a high speed clock signal (having a frequency that is twice a frequency of the main clock signal) may be provided from a memory controller to the DDR memory device.
A DDR memory device (such as a DDR2 memory device for a personal computer or server) may operate at a main frequency of about 400 MHz to provide a data rate of about 800 Mbps. A GDDR (Graphics DDR) memory device (such as a GDDR4 memory device for a graphics card) may operate at a main clock frequency of about 1.25 GHz to provide a data rate of about 2.5 GHz. Moreover, even faster GDDR memory devices (such as a GDDR5 memory device) are proposed to operate, for example, at a main clock frequency of about 2.5 GHz to provide a data rate of about 5 GHz.
In a DDR memory device, the main clock signal (transmitted from the memory controller to the DDR memory device) is used to synchronize transmission of command (CMD) and address (ADD) signals transmitted from the memory controller to the DDR memory device. The high speed clock signal may be generated at the memory controller to have a frequency that is twice the frequency of the main clock signal, and the high speed clock signal may be free running. Moreover, data being written to and/or read from the DDR memory device may be aligned with the high speed clock signal to provide the double data rate.
In a DDR memory device using both a main clock signal and a high speed clock signal, the high speed clock signal may need to be synchronized with the main clock signal to provide proper timing of command, address, and data signals during read and/or write operations. For example, a tuning operation may be used to provide that a rising edge of the main clock signal is aligned with a rising edge of the high speed clock signal (as opposed to a falling edge of the high speed clock signal). More particularly, the high speed clock signal (HSCS) may be divided by 2 to provide a HSCS/2 signal. The HSCS/2 signal may then be compared and aligned with a phase of the main clock signal and tuned so that rising edges of the HSCS/2 signal are aligned with rising edges of the main clock signal. By tuning the HSCH/2 signal, rising edges of the main clock signal may be aligned with rising edges of the high speed clock signal.
Alignment of main and high speed clock signals may be provided in a DDR memory using data training. More particularly, a known data pattern may be written from the controller to a FIFO (First-In-First-Out) buffer of the DDR memory device (not DRAM memory cells). A series of read operations are then performed using different phases of the high speed clock signal to read the known data pattern from the FIFO buffer of the DDR memory device. The phase of the high speed clock signal providing the best performance (e.g., providing a successful read of known data pattern) may then be selected for subsequent read operations. If multiple phases of the high speed clock provide a successful read of the known data pattern, a center one of the passing phases of the high speed clock signal may be selected.
Data training operations, however, may consume time and/or power. Moreover, a frequency divider(s) within a DDR memory may be used to divide the high speed clock signal for internal operation, but an initial value of the frequency divider may be unknown, and the output of the frequency divider may be inverted relative to a desired output. Accordingly, if a clock and/or frequency divider stops after power up (e.g., in a power down mode) with data already aligned, a frequency divider output may be inverted so that another data training operation may be required.